Floating-point units have been constructed for performing arithmetic operations on single-precision floating-point data and double-precision floating-point data. Such floating-point units contain registers for storing floating-point data being processed, logic for processing the sign and exponent parts of floating-point data, mantissa arithmetic units for processing the mantissa, and logic for providing status signals to the processor controlling the floating-point unit.
In certain architectures, conversion of scalar floating-point data from single precision data into 64-bit double precision format occurs within any scalar single precision operation. For single precision numbers in the normal single precision data range, the conversion is very fast and achieved by padding the fraction with trailing zeros and re-biasing the exponent. For single precision denormal numbers, the exponent is re-biased, then the fraction is normalized, and the exponent is adjusted by the normalization shift amount. This requires an additional normalization stage for single precision results on the floating-point unit execution pipeline and on the load data path. State of the art implementations avoid the extra normalization step by storing single precision denormal numbers in an intermediate 65-bit format including the implied integer bit, in which the exponent is re-biased and the fraction is padded with trailing zeros. This additional information makes it possible to distinguish between single precision denormal and double precision normal numbers, both sharing the same exponent. This scheme works well when scalar floating-point data are only consumed by the scalar floating-point unit.